Numerous electronic technologies such as digital computers, video equipment, and telephone systems have facilitated increased productivity and reduced costs in processing information in most areas of business, science, and entertainment. Testing the components is typically an important activity in ensuring proper performance and accurate results. The testing of semiconductor devices often involves performing test operations in accordance with controls referred to as test patterns. Execution of the test patterns typically involves loading and unloading scan chains with test vectors. However, there are a number of factors that can impact testing and traditional testing approaches are often costly and inefficient.
A system on chip (SoC) design is typically composed of several blocks of circuitry, some of which may have similar designs that are used or replicated in different parts of the chips. The several blocks of circuitry are often configured or organized in test blocks or test partitions for purposes of testing the circuitry. Traditional approaches to generating a full set of conventional test patterns targeted at multiple test partitions and executing the test patterns at substantially similar or parallel times is computationally intensive and time consuming. These conventional attempts are often unable to meet limited cost budgets and constrained project schedules.
Transistor feature sizes continue to shrink and smaller transistors allow more circuits to be included in a given die area. Although these technological advances offer a number of advantages, they also create design-for-testability (DFT) challenges. New process technologies are often more sensitive to peak test power and power droop problems. In a complex system-on-chip (SoC), interdependence of the clocking architecture across blocks and overall peak power consumption limits are typically major bottlenecks which hinder or prevent conventional independent parallel testing at a higher clock frequency. In addition, traditional elevated level of power dissipation during testing typically leads to higher die temperature compared to normal functional operation. The higher die temperature can result in improper transistor functions, which in turn cause reliability issues (e.g., due to electro-migration, etc.).